Every StackVM implementation must provide all 128 instructions (opcodes 0x00 to 0x7F) as listed in the table below and with the behavior specified in the associated page (linked under "Base Name").
Every instruction opcode is encoded as 1 byte and StackVM implementations may define up to 128 additional instructions (encoded as opcodes 0x80 to 0xFF).
All Instructions (for which byte order is relevant) are Least
Significant Byte (LSB) first and Most Significant Byte (MSB) last.
That is the LSB has a lower address number than the MSB which is also
known as being
Little-Endian
NOTE: The stack diagram displayed in each instruction's
page represents the push order when read left to right.
In other words, in a stack the left-most item is at the bottom and the
right-most item is at the top.
| Short Name | Description |
|---|---|
| Normal (default) | Available and supported |
| in_design | Will be supported in the future |
| nsm | Not supported but might be soon |
| inf | Implementation Not Finalized |
| deprecated | Supported but not recommended |
| ns | Not supported (No plans for future support) |
| Group Name | Group Code | Sub-Group Name | Sub-Group Code | Base Name | Base Code | Variant | Code |
|---|---|---|---|---|---|---|---|
| Single Special | 0b00000*** | N/A | N/A | NOP | 0b00000000 | NOP | 0b00000000 |
| HLT | 0b00000001 | HLT | 0b00000001 | ||||
| EQ0 | 0b00000010 | EQ0 | 0b00000010 | ||||
| NE0 | 0b00000011 | NE0 | 0b00000011 | ||||
| LT0 | 0b00000100 | LT0 | 0b00000100 | ||||
| LE0 | 0b00000101 | LE0 | 0b00000101 | ||||
| GT0 | 0b00000110 | GT0 | 0b00000110 | ||||
| GE0 | 0b00000111 | GE0 | 0b00000111 | ||||
| Extended | 0b00001*** | N/A | N/A | CONV | 0b00001000 | CONV | 0b00001000 |
| SWAP | 0b00001001 | SWAP | 0b00001001 | ||||
| LOAD | 0b00001010 | LOAD | 0b00001010 | ||||
| STOR | 0b00001011 | STOR | 0b00001011 | ||||
| CALL_E | 0b00001100 | CALL_E | 0b00001100 | ||||
| RET_E | 0b00001101 | RET_E | 0b00001101 | ||||
| SYSREG | 0b00001110 | SYSREG | 0b00001110 | ||||
| INT | 0b00001111 | INT | 0b00001111 | ||||
| Bit/Byte Manip | 0b0001**** | N/A | N/A | LSHIFT | 0b000100** | LSHIFT1 | 0b00010000 |
| LSHIFT2 | 0b00010001 | ||||||
| LSHIFT4 | 0b00010010 | ||||||
| LSHIFT8 | 0b00010011 | ||||||
| RSHIFT | 0b000101** | RSHIFT1 | 0b00010100 | ||||
| RSHIFT2 | 0b00010101 | ||||||
| RSHIFT4 | 0b00010110 | ||||||
| RSHIFT8 | 0b00010111 | ||||||
| LROT | 0b000110** | LROT1 | 0b00011000 | ||||
| LROT2 | 0b00011001 | ||||||
| LROT4 | 0b00011010 | ||||||
| LROT8 | 0b00011011 | ||||||
| RROT | 0b000111** | RROT1 | 0b00011100 | ||||
| RROT2 | 0b00011101 | ||||||
| RROT4 | 0b00011110 | ||||||
| RROT8 | 0b00011111 | ||||||
| ALU Sign Independent |
0b001***** | N/A | N/A | AND | 0b001000** | AND1 | 0b00100000 |
| AND2 | 0b00100001 | ||||||
| AND4 | 0b00100010 | ||||||
| AND8 | 0b00100011 | ||||||
| OR | 0b001001** | OR1 | 0b00100100 | ||||
| OR2 | 0b00100101 | ||||||
| OR4 | 0b00100110 | ||||||
| OR8 | 0b00100111 | ||||||
| NOT | 0b001010** | NOT1 | 0b00101000 | ||||
| NOT2 | 0b00101001 | ||||||
| NOT4 | 0b00101010 | ||||||
| NOT8 | 0b00101011 | ||||||
| XOR | 0b001011** | XOR1 | 0b00101100 | ||||
| XOR2 | 0b00101101 | ||||||
| XOR4 | 0b00101110 | ||||||
| XOR8 | 0b00101111 | ||||||
| ADD | 0b001100** | ADD1 | 0b00110000 | ||||
| ADD2 | 0b00110001 | ||||||
| ADD4 | 0b00110010 | ||||||
| ADD8 | 0b00110011 | ||||||
| SUB | 0b001101** | SUB1 | 0b00110100 | ||||
| SUB2 | 0b00110101 | ||||||
| SUB4 | 0b00110110 | ||||||
| SUB8 | 0b00110111 | ||||||
| ADD_SP | 0b001110** | ADD_SP1 | 0b00111000 | ||||
| ADD_SP2 | 0b00111001 | ||||||
| ADD_SP4 | 0b00111010 | ||||||
| ADD_SP8 | 0b00111011 | ||||||
| RST_SP | 0b001111** | RST_SP1 | 0b00111100 | ||||
| RST_SP2 | 0b00111101 | ||||||
| RST_SP4 | 0b00111110 | ||||||
| RST_SP8 | 0b00111111 | ||||||
| ALU Sign Specific | 0b010***** | N/A | N/A | MUL | 0b01000*** | MUL1 | 0b01000000 |
| MUL1S | 0b01000001 | ||||||
| MUL2 | 0b01000010 | ||||||
| MUL2S | 0b01000011 | ||||||
| MUL4 | 0b01000100 | ||||||
| MUL4S | 0b01000101 | ||||||
| MUL8 | 0b01000110 | ||||||
| MUL8S | 0b01000111 | ||||||
| DIV | 0b01001*** | DIV1 | 0b01001000 | ||||
| DIV1S | 0b01001001 | ||||||
| DIV2 | 0b01001010 | ||||||
| DIV2S | 0b01001011 | ||||||
| DIV4 | 0b01001100 | ||||||
| DIV4S | 0b01001101 | ||||||
| DIV8 | 0b01001110 | ||||||
| DIV8S | 0b01001111 | ||||||
| MOD | 0b01010*** | MOD1 | 0b01010000 | ||||
| MOD1S | 0b01010001 | ||||||
| MOD2 | 0b01010010 | ||||||
| MOD2S | 0b01010011 | ||||||
| MOD4 | 0b01010100 | ||||||
| MOD4S | 0b01010101 | ||||||
| MOD8 | 0b01010110 | ||||||
| MOD8S | 0b01010111 | ||||||
| CMP | 0b01011*** | CMP1 | 0b01011000 | ||||
| CMP1S | 0b01011001 | ||||||
| CMP2 | 0b01011010 | ||||||
| CMP2S | 0b01011011 | ||||||
| CMP4 | 0b01011100 | ||||||
| CMP4S | 0b01011101 | ||||||
| CMP8 | 0b01011110 | ||||||
| CMP8S | 0b01011111 | ||||||
| FPU/CTL Flow | 0b011***** | FPU | 0b0110****/0b01110*** | FADD | 0b011000** | FADD_2 | 0b01100000 |
| FADD_4 | 0b01100001 | ||||||
| FADD_8 | 0b01100010 | ||||||
| FADD_16 | 0b01100011 | ||||||
| FSUB | 0b011001** | FSUB_2 | 0b01100100 | ||||
| FSUB_4 | 0b01100101 | ||||||
| FSUB_8 | 0b01100110 | ||||||
| FSUB_16 | 0b01100111 | ||||||
| FMUL | 0b011010** | FMUL_2 | 0b01101000 | ||||
| FMUL_4 | 0b01101001 | ||||||
| FMUL_8 | 0b01101010 | ||||||
| FMUL_16 | 0b01101011 | ||||||
| FDIV | 0b011011** | FDIV_2 | 0b01101100 | ||||
| FDIV_4 | 0b01101101 | ||||||
| FDIV_8 | 0b01101110 | ||||||
| FDIV_16 | 0b01101111 | ||||||
| FMOD | 0b011100** | FMOD_2 | 0b01110000 | ||||
| FMOD_4 | 0b01110001 | ||||||
| FMOD_8 | 0b01110010 | ||||||
| FMOD_16 | 0b01110011 | ||||||
| FCMP | 0b011101** | FCMP_2 | 0b01110100 | ||||
| FCMP_4 | 0b01110101 | ||||||
| FCMP_8 | 0b01110110 | ||||||
| FCMP_16 | 0b01110111 | ||||||
| Control Flow | 0b01111*** | JMP | 0b011110** | JMP | 0b01111000 | ||
| JMPIF | 0b01111001 | ||||||
| RJMP | 0b01111010 | ||||||
| RJMPIF | 0b01111011 | ||||||
| CALL | 0b0111110* | CALL | 0b01111100 | ||||
| RCALL | 0b01111101 | ||||||
| RET | 0b0111111* | RET | 0b01111110 | ||||
| IRET | 0b01111111 |